Synchronous dynamic random-access memory (SDRAM) chips, including various generations of double data rate (DDR) SDRAMs, use one or more clocks to strobe data onto and off of the memory chip. Data and strobe timing signals are often synchronized to avoid ambiguities in the data bits. As SDRAM bandwidths increase, differential signal propagation delays across the dice may cause a loss of synchronization between data bits and associated clocks.
Modern SDRAM may include one or more on-chip delay-locked loop (DLL) circuits to mitigate the differential delays. DLL-derived strobe circuits may be used to synchronize various SDRAM signals, including an output strobe with data appearing on the output lines. A DLL may delay a clock edge arriving from a distant node by a selected amount. The delayed DLL output is often used to synchronize data and clocks within SDRAM and other memory devices, including data and clocks appearing at the SDRAM output.